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ddbdb3e585
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181 Commits

Author SHA1 Message Date
losfair
ddbdb3e585 Ignore extra arguments. 2019-11-19 02:46:31 +08:00
losfair
06a7e5424b Inline entry trampolines. 2019-11-19 02:39:51 +08:00
losfair
d7308c361d Fix call_indirect on imported functions. 2019-11-19 01:25:01 +08:00
losfair
1eed6ce8f8 Fix CONSTRUCT_STACK_AND_CALL_WASM for aarch64. 2019-11-18 02:06:31 +08:00
losfair
5d2ee4fcc8 Fix floating point comparision involving NaNs. 2019-11-18 01:39:44 +08:00
losfair
cbaa94a7fa Fix movsx(S32, S64). 2019-11-18 01:08:39 +08:00
losfair
08beb99baa Fix popcnt. 2019-11-17 05:15:10 +08:00
losfair
1db6425cd5 Merge remote-tracking branch 'origin/master' into feature/singlepass-aarch64 2019-11-17 04:36:22 +08:00
anb
3b2d751c55 Enable compilation for specific target 
By exposing the target information through `CompilerConfig`,
compiler(only LLVM at the moment) could create a machine with
different CPU feature flags other than current host, which makes it
capable to "cross compile" to some degree.

Update #959
 2019-11-15 18:51:59 -08:00
losfair
08a1dd3e8c Merge master and add documentation. 2019-11-13 14:52:22 +08:00
losfair
e2956e7b1a Run cargo fmt 2019-11-13 14:34:04 +08:00
losfair
47f1e2a4ef Fix parameter loading. 2019-11-13 14:18:21 +08:00
losfair
c552514fd2 Disable NaN canonicalizing on aarch64. 2019-11-13 11:35:44 +08:00
Ivan Enderlin
95706160ee Merge branch 'master' into feat-runtime-core-clos-host-function 2019-11-12 00:55:40 +01:00
Ivan Enderlin
11f34a9285 feat(clif-backend,singlepass-backend) Feed imported functions with FuncCtx.vmctx. 2019-11-12 00:51:57 +01:00
losfair
03c5614203 Rerun cargo fmt 2019-11-11 02:00:16 +08:00
losfair
03a9d1ad60 Cargo fmt 2019-11-11 01:43:16 +08:00
losfair
7d5699c19d Add missing instructions for aarch64. 2019-11-11 01:43:01 +08:00
losfair
899fbed35d Merge master. 2019-11-11 01:42:43 +08:00
Mark McCaskey
a94fabf56e Update supported Rust version to 1.38 2019-11-08 11:40:53 -08:00
losfair
001213716e Add fneg. 2019-11-07 01:30:27 +08:00
losfair
6135a004a4 Add itruncf/fconverti fast path. 2019-11-07 01:11:25 +08:00
Ivan Enderlin
a4ba429ed0 feat(singlepass-backend) Inject FuncCtx to the function pointer of an host function. 2019-11-06 14:48:46 +01:00
losfair
015491ea77 Add floating point instructions. 2019-11-06 01:43:41 +08:00
Ivan Enderlin
edb6cbefca fix(runtime-core) Share the definition of Trampoline across all the backends. 
This patch updates all the backends to use the definition of
`Trampoline` as defined in the `wasmer_runtime_core::typed_func`
module. That way, there is no copy of that type, and as such, it is
easier to avoid regression (a simple `cargo check` does the job).

This patch also formats the `use` statements in the updated files.
 2019-10-30 13:10:34 +01:00
bors[bot]
77527c23ce
Merge #877 
877: Reimplement F32Min, F32Max, F64Min and F64Max. r=nlewycky a=nlewycky

# Description
Reimplement F32Min, F32Max, F64Min and F64Max.

Adds XMM8--15 registers. Adds VMOVA, VBLEND and VXORP, and the VCMPUNORD and VCMPORD comparisons.

Fixes 419 test failures.

Co-authored-by: Nick Lewycky <nick@wasmer.io>
 2019-10-22 17:33:44 +00:00
Ivan Enderlin
e559b54309 fix(singlepass-backend) Use wasmparser from runtime-core. 
The `wasmer-runtime-core` crate re-exports the `wasmparser`
crate. This patch updates the `singlepass-backend` crate to use
`wasmparser` through the `wasmer-runtime-core` crate, which removes a
direct dependency for this crate.
 2019-10-18 11:22:40 +02:00
losfair
cd0b49e661 popcnt for aarch64. 2019-10-18 00:18:15 +08:00
losfair
a057296618 (S32, Imm64, GPR) 2019-10-17 23:45:58 +08:00
losfair
3f35a74b84 Two more mov variants. 2019-10-17 23:40:44 +08:00
losfair
4df7973639 Add mov variants. 2019-10-17 23:34:24 +08:00
losfair
00242cdd7f Fix LEA simulation on aarch64. 2019-10-17 23:00:50 +08:00
losfair
d325635629 Increment aarch64 virtual stack size to 1MB. 2019-10-17 23:00:32 +08:00
Nick Lewycky
4e5d559ab5 Remove dead functions LZCNT and TZCNT. 2019-10-15 13:44:18 -07:00
Nick Lewycky
99f7499a05 Reimplement I32Ctz, I64Clz and I64Ctz without LZCNT or TZCNT. 2019-10-15 13:42:05 -07:00
Nick Lewycky
cafcfd3b50 cargo fmt 2019-10-15 13:07:44 -07:00
Nick Lewycky
cf3d2a830d Reimplement I32Clz without relying on LZCNT. 2019-10-15 12:50:59 -07:00
losfair
3de0c7763f Skip inline non-instruction data. 2019-10-15 22:12:08 +08:00
losfair
81d538ade2 Fix disp < 0 case. 2019-10-15 22:00:33 +08:00
losfair
ee88c459e5 Allow arbitrary size of disp. 2019-10-15 21:55:04 +08:00
Nick Lewycky
26a4f073f0 Implement F64Min and F64Max. 2019-10-14 14:15:18 -07:00
Nick Lewycky
06ffb00deb Reimplement F32Max. 2019-10-14 14:07:30 -07:00
Nick Lewycky
b886a41a85 Use temp_gprs instead of hard-coding RAX/RDX. 2019-10-14 13:53:30 -07:00
Nick Lewycky
5cee23455d Release the registers we acquire. Reformat. 2019-10-14 13:51:03 -07:00
Nick Lewycky
336dab7fd9 Don't use utility functions in F32Min implementation. 2019-10-14 13:46:55 -07:00
Nick Lewycky
765e1d3b9e Add XMM8--XMM15. These were added in x64. 2019-10-14 13:46:55 -07:00
Nick Lewycky
4b89e01806 Remove commented-out code that I added so as to not lose its history in git. Apply trivial cleanups and reformat. 
Remove expected test failure entries that are fixed so far.
 2019-10-14 13:46:55 -07:00
Nick Lewycky
963148fdce Fix F32Min for all cases including NaNs. 2019-10-14 13:46:55 -07:00
Nick Lewycky
8b937afc1f Add comments to indicate the implemention we'd like to have, but can't right now. 2019-10-14 13:46:55 -07:00
Nick Lewycky
0f712c90ab Don't allocate another register when it's safe to reuse dst. 2019-10-14 13:46:55 -07:00