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207 Commits

Author SHA1 Message Date
bors[bot]
8ffd380006
Merge #973 
973: Add sign extension spec tests; add sign extension to singlepass r=nlewycky a=MarkMcCaskey

Adds missing spectests from official repo, implements instructions for singlepass

# Review

- [ ] Add a short description of the the change to the CHANGELOG.md file


Co-authored-by: Mark McCaskey <mark@wasmer.io>
Co-authored-by: Mark McCaskey <5770194+markmccaskey@users.noreply.github.com>
 2019-11-18 22:16:49 +00:00
Mark McCaskey
8a096a09e4 Remove extra register use in sign extension instructions 2019-11-18 11:47:58 -08:00
bors[bot]
e568c4a374
Merge #972 
972: Prepare for 0.10.2 release r=MarkMcCaskey a=MarkMcCaskey



Co-authored-by: Mark McCaskey <mark@wasmer.io>
 2019-11-18 19:44:33 +00:00
Mark McCaskey
344132cc89
Merge branch 'master' into feature/singlepass-sign-extension 2019-11-18 11:38:12 -08:00
Mark McCaskey
8b6a7b77fc Clean up from feedback 2019-11-18 11:36:49 -08:00
Mark McCaskey
2cbc748188 Revert "Update Rust version to 1.39.0." 2019-11-18 09:59:07 -08:00
losfair
021a75244e Reformat code for rust 1.39. 2019-11-17 04:39:39 +08:00
Mark McCaskey
7631aee4f4 Add sign extension spec tests; add sign extension to singlepass 2019-11-15 21:54:34 -08:00
anb
3b2d751c55 Enable compilation for specific target 
By exposing the target information through `CompilerConfig`,
compiler(only LLVM at the moment) could create a machine with
different CPU feature flags other than current host, which makes it
capable to "cross compile" to some degree.

Update #959
 2019-11-15 18:51:59 -08:00
Mark McCaskey
cebcb4c927 Prepare for 0.10.2 release 2019-11-15 14:55:53 -08:00
bors[bot]
fff16c08d0
Merge #965 
965: Add categories and keywords to `Cargo.toml`s r=MarkMcCaskey a=MarkMcCaskey



Co-authored-by: Mark McCaskey <mark@wasmer.io>
 2019-11-13 23:47:56 +00:00
Mark McCaskey
9127eaf825 Add categories and keywords to Cargo.tomls 2019-11-13 15:46:09 -08:00
Ivan Enderlin
89859a9ab5 Merge branch 'master' into feat-runtime-core-clos-host-function 2019-11-12 14:36:33 +01:00
Mark McCaskey
69950d9e5f Prepare for 0.10.1 release 2019-11-11 16:22:37 -08:00
Ivan Enderlin
95706160ee Merge branch 'master' into feat-runtime-core-clos-host-function 2019-11-12 00:55:40 +01:00
Ivan Enderlin
11f34a9285 feat(clif-backend,singlepass-backend) Feed imported functions with FuncCtx.vmctx. 2019-11-12 00:51:57 +01:00
Mark McCaskey
0a216c0779 Prepare for 0.10.0 release 2019-11-11 12:13:53 -08:00
Mark McCaskey
a94fabf56e Update supported Rust version to 1.38 2019-11-08 11:40:53 -08:00
Ivan Enderlin
a4ba429ed0 feat(singlepass-backend) Inject FuncCtx to the function pointer of an host function. 2019-11-06 14:48:46 +01:00
Ivan Enderlin
edb6cbefca fix(runtime-core) Share the definition of Trampoline across all the backends. 
This patch updates all the backends to use the definition of
`Trampoline` as defined in the `wasmer_runtime_core::typed_func`
module. That way, there is no copy of that type, and as such, it is
easier to avoid regression (a simple `cargo check` does the job).

This patch also formats the `use` statements in the updated files.
 2019-10-30 13:10:34 +01:00
Mark McCaskey
82f258b888 Prepare for 0.9.0 release 2019-10-23 13:40:35 -07:00
bors[bot]
77527c23ce
Merge #877 
877: Reimplement F32Min, F32Max, F64Min and F64Max. r=nlewycky a=nlewycky

# Description
Reimplement F32Min, F32Max, F64Min and F64Max.

Adds XMM8--15 registers. Adds VMOVA, VBLEND and VXORP, and the VCMPUNORD and VCMPORD comparisons.

Fixes 419 test failures.

Co-authored-by: Nick Lewycky <nick@wasmer.io>
 2019-10-22 17:33:44 +00:00
Ivan Enderlin
e559b54309 fix(singlepass-backend) Use wasmparser from runtime-core. 
The `wasmer-runtime-core` crate re-exports the `wasmparser`
crate. This patch updates the `singlepass-backend` crate to use
`wasmparser` through the `wasmer-runtime-core` crate, which removes a
direct dependency for this crate.
 2019-10-18 11:22:40 +02:00
Nick Lewycky
4e5d559ab5 Remove dead functions LZCNT and TZCNT. 2019-10-15 13:44:18 -07:00
Nick Lewycky
99f7499a05 Reimplement I32Ctz, I64Clz and I64Ctz without LZCNT or TZCNT. 2019-10-15 13:42:05 -07:00
Nick Lewycky
cafcfd3b50 cargo fmt 2019-10-15 13:07:44 -07:00
Nick Lewycky
cf3d2a830d Reimplement I32Clz without relying on LZCNT. 2019-10-15 12:50:59 -07:00
Nick Lewycky
26a4f073f0 Implement F64Min and F64Max. 2019-10-14 14:15:18 -07:00
Nick Lewycky
06ffb00deb Reimplement F32Max. 2019-10-14 14:07:30 -07:00
Nick Lewycky
b886a41a85 Use temp_gprs instead of hard-coding RAX/RDX. 2019-10-14 13:53:30 -07:00
Nick Lewycky
5cee23455d Release the registers we acquire. Reformat. 2019-10-14 13:51:03 -07:00
Nick Lewycky
336dab7fd9 Don't use utility functions in F32Min implementation. 2019-10-14 13:46:55 -07:00
Nick Lewycky
765e1d3b9e Add XMM8--XMM15. These were added in x64. 2019-10-14 13:46:55 -07:00
Nick Lewycky
4b89e01806 Remove commented-out code that I added so as to not lose its history in git. Apply trivial cleanups and reformat. 
Remove expected test failure entries that are fixed so far.
 2019-10-14 13:46:55 -07:00
Nick Lewycky
963148fdce Fix F32Min for all cases including NaNs. 2019-10-14 13:46:55 -07:00
Nick Lewycky
8b937afc1f Add comments to indicate the implemention we'd like to have, but can't right now. 2019-10-14 13:46:55 -07:00
Nick Lewycky
0f712c90ab Don't allocate another register when it's safe to reuse dst. 2019-10-14 13:46:55 -07:00
Nick Lewycky
b75e5c0c7c When we know RDX is unavailable, use RAX instead. Should be fine here. 2019-10-14 13:46:55 -07:00
Nick Lewycky
d6eba03a2f Remove loc1/loc2. That intended refactoring didn't work out. 2019-10-14 13:46:55 -07:00
Nick Lewycky
555d933057 Initial commit, reimplementation of F32Min. Fixes F32Min(negative_zero, zero) issue. 
Also removes some previously-fixed i32 and i64 exclusions from the tests.
 2019-10-14 13:46:55 -07:00
nlewycky
f63c706abc
Merge branch 'master' into feature/singlepass-atomicops 2019-10-02 16:46:59 -07:00
Nick Lewycky
ab76c2357f Delete dead (commented out) code. NFC. 2019-10-02 16:31:11 -07:00
Nick Lewycky
8e63d54fdb cargo fmt 2019-10-02 16:31:11 -07:00
Nick Lewycky
83b678bc36 Give this function a better name. 2019-10-02 16:31:11 -07:00
Nick Lewycky
11c5e0d71d Make the panics a bit more descriptive. 2019-10-02 16:31:11 -07:00
Nick Lewycky
ba68cfc2c6 Finish atomic operations for singlepass, excluding wait and notify. 2019-10-02 16:31:11 -07:00
Nick Lewycky
bc7e017188 Add atomic.rmw operations, excluding xchg and cmpxchg. 
Sizes are now ordered, to facilitate an assertion that one size is less (smaller) than another.

panic! error messages are provided for remaining emitter functions.
 2019-10-02 16:31:11 -07:00
Nick Lewycky
f021d59a0b Refactor out a compare-and-swap loop function. 2019-10-02 16:31:11 -07:00
Nick Lewycky
cd1d06f5a5 Initial working implementation of I32AtomicRmwAnd! 
Adds the ability to reserve a specific temp-gpr register. Needed for CMPXCHG which always uses RAX.
 2019-10-02 16:31:11 -07:00
Nick Lewycky
6937019b65 Use a compare-and-swap loop for AND. 
BUG: This might allocate RAX twice.
 2019-10-02 16:31:10 -07:00