mirror of
https://github.com/fluencelabs/wasmer
synced 2024-12-13 14:25:32 +00:00
64-bit operators.
This commit is contained in:
losfair
parent
fa61b66516
commit
bd7698e1f2
@ -383,18 +383,20 @@ impl X64FunctionCode {
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}
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/// Emits a unary operator.
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fn emit_unop_i32<F: FnOnce(&mut Assembler, &ValueStack, Register)>(
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fn emit_unop<F: FnOnce(&mut Assembler, &ValueStack, Register)>(
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assembler: &mut Assembler,
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value_stack: &mut ValueStack,
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f: F,
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in_ty: WpType,
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out_ty: WpType,
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) -> Result<(), CodegenError> {
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let a = value_stack.pop()?;
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if a.ty != WpType::I32 {
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if a.ty != in_ty {
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return Err(CodegenError {
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message: "unop(i32) type mismatch",
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});
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}
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value_stack.push(WpType::I32);
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value_stack.push(out_ty);
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match a.location {
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ValueLocation::Register(x) => {
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@ -404,12 +406,12 @@ impl X64FunctionCode {
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ValueLocation::Stack => {
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dynasm!(
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assembler
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; mov eax, [rsp]
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; mov rax, [rsp]
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);
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f(assembler, value_stack, Register::RAX);
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dynasm!(
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assembler
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; mov [rsp], eax
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; mov [rsp], rax
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);
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}
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}
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@ -417,21 +419,39 @@ impl X64FunctionCode {
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Ok(())
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}
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/// Emits a binary operator.
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///
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/// Guarantees that the first Register parameter to callback `f` will never be `Register::RAX`.
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fn emit_binop_i32<F: FnOnce(&mut Assembler, &ValueStack, Register, Register)>(
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fn emit_unop_i32<F: FnOnce(&mut Assembler, &ValueStack, Register)>(
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assembler: &mut Assembler,
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value_stack: &mut ValueStack,
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f: F,
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) -> Result<(), CodegenError> {
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Self::emit_unop(assembler, value_stack, f, WpType::I32, WpType::I32)
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}
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fn emit_unop_i64<F: FnOnce(&mut Assembler, &ValueStack, Register)>(
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assembler: &mut Assembler,
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value_stack: &mut ValueStack,
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f: F,
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) -> Result<(), CodegenError> {
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Self::emit_unop(assembler, value_stack, f, WpType::I64, WpType::I64)
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}
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/// Emits a binary operator.
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///
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/// Guarantees that the first Register parameter to callback `f` will never be `Register::RAX`.
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fn emit_binop<F: FnOnce(&mut Assembler, &ValueStack, Register, Register)>(
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assembler: &mut Assembler,
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value_stack: &mut ValueStack,
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f: F,
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in_ty: WpType,
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out_ty: WpType,
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) -> Result<(), CodegenError> {
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let (a, b) = value_stack.pop2()?;
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if a.ty != WpType::I32 || b.ty != WpType::I32 {
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if a.ty != in_ty || b.ty != in_ty {
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return Err(CodegenError {
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message: "binop(i32) type mismatch",
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});
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}
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value_stack.push(WpType::I32);
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value_stack.push(out_ty);
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if a.location.is_register() && b.location.is_register() {
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// output is in a_reg.
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@ -458,13 +478,13 @@ impl X64FunctionCode {
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dynasm!(
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assembler
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; push rcx
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; mov ecx, [rsp + 16]
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; mov eax, [rsp + 8]
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; mov rcx, [rsp + 16]
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; mov rax, [rsp + 8]
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);
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f(assembler, value_stack, Register::RCX, Register::RAX);
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dynasm!(
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assembler
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; mov [rsp + 16], ecx
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; mov [rsp + 16], rcx
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; pop rcx
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; add rsp, 8
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);
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@ -473,6 +493,22 @@ impl X64FunctionCode {
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Ok(())
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}
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fn emit_binop_i32<F: FnOnce(&mut Assembler, &ValueStack, Register, Register)>(
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assembler: &mut Assembler,
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value_stack: &mut ValueStack,
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f: F,
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) -> Result<(), CodegenError> {
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Self::emit_binop(assembler, value_stack, f, WpType::I32, WpType::I32)
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}
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fn emit_binop_i64<F: FnOnce(&mut Assembler, &ValueStack, Register, Register)>(
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assembler: &mut Assembler,
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value_stack: &mut ValueStack,
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f: F,
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) -> Result<(), CodegenError> {
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Self::emit_binop(assembler, value_stack, f, WpType::I64, WpType::I64)
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}
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fn emit_div_i32(
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assembler: &mut Assembler,
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value_stack: &ValueStack,
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@ -567,6 +603,27 @@ impl X64FunctionCode {
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);
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}
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fn emit_cmp_i64<F: FnOnce(&mut Assembler)>(
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assembler: &mut Assembler,
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left: Register,
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right: Register,
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f: F,
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) {
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dynasm!(
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assembler
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; cmp Rq(left as u8), Rq(right as u8)
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);
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f(assembler);
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dynasm!(
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assembler
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; xor Rq(left as u8), Rq(left as u8)
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; jmp >label_end
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; label_true:
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; mov Rq(left as u8), 1
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; label_end:
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);
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}
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fn emit_peek_into_ax(
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assembler: &mut Assembler,
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value_stack: &ValueStack,
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@ -1626,6 +1683,308 @@ impl FunctionCodeGenerator for X64FunctionCode {
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},
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)?;
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}
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Operator::I64Const { value } => {
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let location = self.value_stack.push(WpType::I64);
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match location {
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ValueLocation::Register(x) => {
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let reg = Register::from_scratch_reg(x);
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dynasm!(
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assembler
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; mov Rq(reg as u8), QWORD value
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);
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}
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ValueLocation::Stack => {
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dynasm!(
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assembler
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; mov rax, QWORD value
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; push rax
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);
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}
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}
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}
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Operator::I64Add => {
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Self::emit_binop_i64(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; add Rq(left as u8), Rq(right as u8)
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)
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},
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)?;
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}
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Operator::I64Sub => {
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Self::emit_binop_i64(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; sub Rq(left as u8), Rq(right as u8)
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)
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},
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)?;
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}
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Operator::I64Mul => {
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Self::emit_binop_i64(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; imul Rq(left as u8), Rq(right as u8)
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)
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},
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)?;
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}
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Operator::I64DivU => {
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unimplemented!();
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}
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Operator::I64DivS => {
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unimplemented!();
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}
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Operator::I64RemU => {
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unimplemented!();
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}
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Operator::I64RemS => {
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unimplemented!();
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}
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Operator::I64And => {
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Self::emit_binop_i64(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; and Rq(left as u8), Rq(right as u8)
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);
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},
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)?;
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}
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Operator::I64Or => {
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Self::emit_binop_i64(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; or Rq(left as u8), Rq(right as u8)
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);
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},
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)?;
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}
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Operator::I64Eq => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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dynasm!(
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assembler
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; cmp Rq(left as u8), Rq(right as u8)
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; lahf
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; shr ax, 14
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; and eax, 1
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; mov Rd(left as u8), eax
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);
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64Eqz => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; cmp Rq(reg as u8), 0
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; lahf
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; shr ax, 14
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; and eax, 1
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);
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if reg != Register::RAX {
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dynasm!(
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assembler
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; mov Rd(reg as u8), eax
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);
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}
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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// Comparison operators.
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// https://en.wikibooks.org/wiki/X86_Assembly/Control_Flow
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// TODO: Is reading flag register directly faster?
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Operator::I64LtS => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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Self::emit_cmp_i64(assembler, left, right, |assembler| {
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dynasm!(
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assembler
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; jl >label_true
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);
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});
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64LeS => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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Self::emit_cmp_i64(assembler, left, right, |assembler| {
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dynasm!(
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assembler
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; jle >label_true
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);
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});
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64GtS => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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Self::emit_cmp_i64(assembler, left, right, |assembler| {
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dynasm!(
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assembler
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; jg >label_true
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);
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});
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64GeS => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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Self::emit_cmp_i64(assembler, left, right, |assembler| {
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dynasm!(
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assembler
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; jge >label_true
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);
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});
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64LtU => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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Self::emit_cmp_i64(assembler, left, right, |assembler| {
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dynasm!(
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assembler
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; jb >label_true
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);
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});
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64LeU => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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Self::emit_cmp_i64(assembler, left, right, |assembler| {
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dynasm!(
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assembler
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; jbe >label_true
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);
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});
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64GtU => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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Self::emit_cmp_i64(assembler, left, right, |assembler| {
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dynasm!(
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assembler
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; ja >label_true
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);
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});
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64GeU => {
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Self::emit_binop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, left, right| {
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Self::emit_cmp_i64(assembler, left, right, |assembler| {
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dynasm!(
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assembler
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; jae >label_true
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);
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});
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},
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WpType::I64,
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WpType::I32,
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)?;
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}
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Operator::I64ExtendSI32 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
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; movsx Rq(reg as u8), Rd(reg as u8)
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);
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},
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WpType::I32,
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WpType::I64,
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)?;
|
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}
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Operator::I64ExtendUI32 => {
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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// FIXME: Is it correct to do nothing here?
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},
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WpType::I32,
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WpType::I64,
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)?;
|
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}
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Operator::I32WrapI64 => {
|
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Self::emit_unop(
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assembler,
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&mut self.value_stack,
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|assembler, value_stack, reg| {
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dynasm!(
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assembler
|
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; mov Rd(reg as u8), Rd(reg as u8) // clear upper 32 bits
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);
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},
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WpType::I64,
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WpType::I32,
|
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)?;
|
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}
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Operator::Block { ty } => {
|
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self.control_stack
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.as_mut()
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@ -2005,6 +2364,149 @@ impl FunctionCodeGenerator for X64FunctionCode {
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WpType::I32,
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)?;
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}
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Operator::I64Load { memarg } => {
|
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Self::emit_memory_load(
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assembler,
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&mut self.value_stack,
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|assembler, reg| {
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dynasm!(
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assembler
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; mov Rq(reg as u8), [Rq(reg as u8) + memarg.offset as i32]
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);
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},
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WpType::I64,
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)?;
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}
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Operator::I64Load8U { memarg } => {
|
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Self::emit_memory_load(
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assembler,
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&mut self.value_stack,
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|assembler, reg| {
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dynasm!(
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assembler
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; movzx Rq(reg as u8), BYTE [Rq(reg as u8) + memarg.offset as i32]
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);
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},
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WpType::I64,
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)?;
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}
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Operator::I64Load8S { memarg } => {
|
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Self::emit_memory_load(
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assembler,
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&mut self.value_stack,
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|assembler, reg| {
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dynasm!(
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assembler
|
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; movsx Rq(reg as u8), BYTE [Rq(reg as u8) + memarg.offset as i32]
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);
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},
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WpType::I64,
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)?;
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}
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Operator::I64Load16U { memarg } => {
|
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Self::emit_memory_load(
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assembler,
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&mut self.value_stack,
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|assembler, reg| {
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dynasm!(
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assembler
|
||||
; movzx Rq(reg as u8), WORD [Rq(reg as u8) + memarg.offset as i32]
|
||||
);
|
||||
},
|
||||
WpType::I64,
|
||||
)?;
|
||||
}
|
||||
Operator::I64Load16S { memarg } => {
|
||||
Self::emit_memory_load(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movsx Rq(reg as u8), WORD [Rq(reg as u8) + memarg.offset as i32]
|
||||
);
|
||||
},
|
||||
WpType::I64,
|
||||
)?;
|
||||
}
|
||||
Operator::I64Load32U { memarg } => {
|
||||
Self::emit_memory_load(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; mov Rd(reg as u8), DWORD [Rq(reg as u8) + memarg.offset as i32]
|
||||
);
|
||||
},
|
||||
WpType::I64,
|
||||
)?;
|
||||
}
|
||||
Operator::I64Load32S { memarg } => {
|
||||
Self::emit_memory_load(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; movsx Rq(reg as u8), DWORD [Rq(reg as u8) + memarg.offset as i32]
|
||||
);
|
||||
},
|
||||
WpType::I64,
|
||||
)?;
|
||||
}
|
||||
Operator::I64Store { memarg } => {
|
||||
Self::emit_memory_store(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, addr_reg, value_reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; mov [Rq(addr_reg as u8) + memarg.offset as i32], Rq(value_reg as u8)
|
||||
);
|
||||
},
|
||||
WpType::I64,
|
||||
)?;
|
||||
}
|
||||
Operator::I64Store8 { memarg } => {
|
||||
Self::emit_memory_store(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, addr_reg, value_reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; mov [Rq(addr_reg as u8) + memarg.offset as i32], Rb(value_reg as u8)
|
||||
);
|
||||
},
|
||||
WpType::I64,
|
||||
)?;
|
||||
}
|
||||
Operator::I64Store16 { memarg } => {
|
||||
Self::emit_memory_store(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, addr_reg, value_reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; mov [Rq(addr_reg as u8) + memarg.offset as i32], Rw(value_reg as u8)
|
||||
);
|
||||
},
|
||||
WpType::I64,
|
||||
)?;
|
||||
}
|
||||
Operator::I64Store32 { memarg } => {
|
||||
Self::emit_memory_store(
|
||||
assembler,
|
||||
&mut self.value_stack,
|
||||
|assembler, addr_reg, value_reg| {
|
||||
dynasm!(
|
||||
assembler
|
||||
; mov [Rq(addr_reg as u8) + memarg.offset as i32], Rd(value_reg as u8)
|
||||
);
|
||||
},
|
||||
WpType::I64,
|
||||
)?;
|
||||
}
|
||||
_ => unimplemented!(),
|
||||
}
|
||||
Ok(())
|
||||
|
||||
Loading…
Reference in New Issue
Block a user