From 70450305323ecd1055223110b0843d6f64861f08 Mon Sep 17 00:00:00 2001 From: Nick Lewycky Date: Thu, 11 Jul 2019 14:48:07 -0700 Subject: [PATCH] Try a new list of optimization passes. A few notes: a) the inliner doesn't help because all the calls are indirect and not even opt -O2 can figure out which functions they're actually calling. b) aggressive instruction combining is not a super-set of the instruction combiner. Instcombine is made up of a large number (probably 10,000s) of patterns, and some particularly slow ones were taken out and moved to the aggressive instruction combiner. Aggressive instcombine *only* runs that handful of optimizations, which fired zero times on our example wasm files. c) NewGVN is not ready for production, it has asserts that fire when building sqlite or cowsay. This is why sqlite didn't build with the llvm backend. d) Scalar-replacement-of-aggregates (sroa) is a strict superset of promote-memory-to-registers (mem2reg), and you probably want sroa because it's usually faster. It also fires 10,000s more times than mem2reg on lua.wasm. e) Aggressive-dead-code-elimination was only deleting as much regular dead-code-elimination, but is slower because it depends on a postdominator tree (PDT) analysis that. Other passes don't need PDT so we'll have to build it for just this one pass (as opposed to regular dominator-tree which is reused by many passes). I've replaced this with bit-tracking dead-code-elimination which deletes more code than dce/adce. --- lib/llvm-backend/src/code.rs | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/lib/llvm-backend/src/code.rs b/lib/llvm-backend/src/code.rs index 7fe98805f..f1962639d 100644 --- a/lib/llvm-backend/src/code.rs +++ b/lib/llvm-backend/src/code.rs @@ -2583,13 +2583,19 @@ impl ModuleCodeGenerator if cfg!(test) { pass_manager.add_verifier_pass(); } - pass_manager.add_function_inlining_pass(); - pass_manager.add_promote_memory_to_register_pass(); + pass_manager.add_lower_expect_intrinsic_pass(); + pass_manager.add_scalar_repl_aggregates_pass(); + pass_manager.add_instruction_combining_pass(); pass_manager.add_cfg_simplification_pass(); - pass_manager.add_aggressive_inst_combiner_pass(); - pass_manager.add_merged_load_store_motion_pass(); - pass_manager.add_new_gvn_pass(); - pass_manager.add_aggressive_dce_pass(); + pass_manager.add_gvn_pass(); + pass_manager.add_jump_threading_pass(); + pass_manager.add_correlated_value_propagation_pass(); + pass_manager.add_sccp_pass(); + pass_manager.add_instruction_combining_pass(); + pass_manager.add_reassociate_pass(); + pass_manager.add_cfg_simplification_pass(); + pass_manager.add_bit_tracking_dce_pass(); + pass_manager.add_slp_vectorize_pass(); pass_manager.run_on_module(&self.module); // self.module.print_to_stderr();