mirror of
https://github.com/fluencelabs/wasmer
synced 2024-12-04 18:10:18 +00:00
Integer subset done.
This commit is contained in:
losfair
parent
a124d87d0f
commit
3dadbc15c9
@ -264,6 +264,62 @@ macro_rules! binop_all_nofp {
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};
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}
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macro_rules! binop_shift {
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($ins:ident, $assembler:tt, $sz:expr, $src:expr, $dst:expr, $otherwise:block) => {
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match ($sz, $src, $dst) {
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(Size::S32, Location::Imm8(imm), Location::GPR(dst)) => {
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assert!(imm < 32);
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dynasm!($assembler ; $ins W(map_gpr(dst).x()), W(map_gpr(dst).x()), imm as u32);
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},
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(Size::S32, Location::Imm8(imm), Location::Memory(base, disp)) => {
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assert!(imm < 32);
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assert!(disp >= 0);
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dynasm!($assembler
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; ldr w_tmp1, [X(map_gpr(base).x()), disp as u32]
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; $ins w_tmp1, w_tmp1, imm as u32
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; str w_tmp1, [X(map_gpr(base).x()), disp as u32]
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);
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},
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(Size::S32, Location::GPR(GPR::RCX), Location::GPR(dst)) => {
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dynasm!($assembler ; $ins W(map_gpr(dst).x()), W(map_gpr(dst).x()), W(map_gpr(GPR::RCX).x()));
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},
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(Size::S32, Location::GPR(GPR::RCX), Location::Memory(base, disp)) => {
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assert!(disp >= 0);
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dynasm!($assembler
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; ldr w_tmp1, [X(map_gpr(base).x()), disp as u32]
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; $ins w_tmp1, w_tmp1, W(map_gpr(GPR::RCX).x())
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; str w_tmp1, [X(map_gpr(base).x()), disp as u32]
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);
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},
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(Size::S64, Location::Imm8(imm), Location::GPR(dst)) => {
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assert!(imm < 32);
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dynasm!($assembler ; $ins X(map_gpr(dst).x()), X(map_gpr(dst).x()), imm as u32);
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},
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(Size::S64, Location::Imm8(imm), Location::Memory(base, disp)) => {
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assert!(imm < 32);
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assert!(disp >= 0);
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dynasm!($assembler
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; ldr x_tmp1, [X(map_gpr(base).x()), disp as u32]
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; $ins x_tmp1, x_tmp1, imm as u32
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; str x_tmp1, [X(map_gpr(base).x()), disp as u32]
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);
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},
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(Size::S64, Location::GPR(GPR::RCX), Location::GPR(dst)) => {
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dynasm!($assembler ; $ins X(map_gpr(dst).x()), X(map_gpr(dst).x()), X(map_gpr(GPR::RCX).x()));
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},
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(Size::S64, Location::GPR(GPR::RCX), Location::Memory(base, disp)) => {
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assert!(disp >= 0);
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dynasm!($assembler
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; ldr x_tmp1, [X(map_gpr(base).x()), disp as u32]
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; $ins x_tmp1, x_tmp1, X(map_gpr(GPR::RCX).x())
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; str x_tmp1, [X(map_gpr(base).x()), disp as u32]
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);
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},
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_ => $otherwise
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}
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}
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}
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impl Emitter for Assembler {
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type Label = DynamicLabel;
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type Offset = AssemblyOffset;
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@ -629,26 +685,155 @@ impl Emitter for Assembler {
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}
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fn emit_div(&mut self, sz: Size, divisor: Location) {
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unimplemented!("instruction")
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match sz {
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Size::S32 => {
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match divisor {
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Location::GPR(x) => dynasm!(
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self
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; mov w_tmp1, W(map_gpr(x).x())
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),
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(
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self
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; ldr w_tmp1, [X(map_gpr(base).x()), disp as u32]
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)
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}
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_ => unreachable!()
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}
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dynasm!(
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self
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; mov w_tmp2, W(map_gpr(GPR::RAX).x())
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; udiv W(map_gpr(GPR::RAX).x()), w_tmp2, w_tmp1
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; msub W(map_gpr(GPR::RDX).x()), W(map_gpr(GPR::RAX).x()), w_tmp1, w_tmp2
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)
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}
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Size::S64 => {
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match divisor {
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Location::GPR(x) => dynasm!(
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self
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; mov x_tmp1, X(map_gpr(x).x())
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),
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(
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self
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; ldr x_tmp1, [X(map_gpr(base).x()), disp as u32]
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)
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}
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_ => unreachable!()
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}
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dynasm!(
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self
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; mov x_tmp2, X(map_gpr(GPR::RAX).x())
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; udiv X(map_gpr(GPR::RAX).x()), x_tmp2, x_tmp1
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; msub X(map_gpr(GPR::RDX).x()), X(map_gpr(GPR::RAX).x()), x_tmp1, x_tmp2
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)
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}
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_ => unreachable!()
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}
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}
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fn emit_idiv(&mut self, sz: Size, divisor: Location) {
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unimplemented!("instruction")
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match sz {
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Size::S32 => {
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match divisor {
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Location::GPR(x) => dynasm!(
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self
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; mov w_tmp1, W(map_gpr(x).x())
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),
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(
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self
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; ldr w_tmp1, [X(map_gpr(base).x()), disp as u32]
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)
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}
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_ => unreachable!()
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}
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dynasm!(
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self
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; mov w_tmp2, W(map_gpr(GPR::RAX).x())
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; sdiv W(map_gpr(GPR::RAX).x()), w_tmp2, w_tmp1
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; msub W(map_gpr(GPR::RDX).x()), W(map_gpr(GPR::RAX).x()), w_tmp1, w_tmp2
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)
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}
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Size::S64 => {
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match divisor {
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Location::GPR(x) => dynasm!(
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self
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; mov x_tmp1, X(map_gpr(x).x())
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),
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(
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self
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; ldr x_tmp1, [X(map_gpr(base).x()), disp as u32]
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)
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}
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_ => unreachable!()
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}
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dynasm!(
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self
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; mov x_tmp2, X(map_gpr(GPR::RAX).x())
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; sdiv X(map_gpr(GPR::RAX).x()), x_tmp2, x_tmp1
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; msub X(map_gpr(GPR::RDX).x()), X(map_gpr(GPR::RAX).x()), x_tmp1, x_tmp2
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)
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}
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_ => unreachable!()
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}
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}
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fn emit_shl(&mut self, sz: Size, src: Location, dst: Location) {
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//binop_all_nofp!(ushl, self, sz, src, dst, { unreachable!("shl") });
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unimplemented!("instruction")
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binop_shift!(lsl, self, sz, src, dst, { unreachable!("shl") });
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}
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fn emit_shr(&mut self, sz: Size, src: Location, dst: Location) {
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unimplemented!("instruction")
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binop_shift!(lsr, self, sz, src, dst, { unreachable!("shr") });
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}
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fn emit_sar(&mut self, sz: Size, src: Location, dst: Location) {
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unimplemented!("instruction")
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binop_shift!(asr, self, sz, src, dst, { unreachable!("sar") });
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}
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fn emit_rol(&mut self, sz: Size, src: Location, dst: Location) {
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unimplemented!("instruction")
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// TODO: We are changing content of `src` (possibly RCX) here. Will this break any assumptions?
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match sz {
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Size::S32 => {
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match src {
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Location::Imm8(x) => {
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assert!(x < 32);
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binop_shift!(ror, self, sz, Location::Imm8(32 - x), dst, { unreachable!("rol") });
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}
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Location::GPR(GPR::RCX) => {
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dynasm!(
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self
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; mov w_tmp1, 32
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; sub W(map_gpr(GPR::RCX).x()), w_tmp1, W(map_gpr(GPR::RCX).x())
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);
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binop_shift!(ror, self, sz, src, dst, { unreachable!("rol") });
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}
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_ => unreachable!()
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}
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}
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Size::S64 => {
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match src {
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Location::Imm8(x) => {
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assert!(x < 64);
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binop_shift!(ror, self, sz, Location::Imm8(64 - x), dst, { unreachable!("rol") });
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}
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Location::GPR(GPR::RCX) => {
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dynasm!(
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self
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; mov x_tmp1, 64
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; sub X(map_gpr(GPR::RCX).x()), x_tmp1, X(map_gpr(GPR::RCX).x())
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);
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binop_shift!(ror, self, sz, src, dst, { unreachable!("rol") });
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}
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_ => unreachable!()
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}
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}
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_ => unreachable!()
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}
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}
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fn emit_ror(&mut self, sz: Size, src: Location, dst: Location) {
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unimplemented!("instruction")
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binop_shift!(ror, self, sz, src, dst, { unreachable!("ror") });
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}
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fn emit_and(&mut self, sz: Size, src: Location, dst: Location) {
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binop_all_nofp!(and, self, sz, src, dst, { unreachable!("and") });
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@ -657,89 +842,16 @@ impl Emitter for Assembler {
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binop_all_nofp!(orr, self, sz, src, dst, { unreachable!("or") });
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}
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fn emit_lzcnt(&mut self, sz: Size, src: Location, dst: Location) {
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match sz {
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Size::S32 => {
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match src {
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Location::Imm32(x) => dynasm!(self
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; b >after
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; data:
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; .dword x as i32
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; after:
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; ldr w_tmp2, <data
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; clz w_tmp1, w_tmp2
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),
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Location::GPR(x) => dynasm!(self
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; clz w_tmp1, W(map_gpr(x).x())
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),
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(self
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; ldr w_tmp1, [X(map_gpr(base).x()), disp as u32]
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; clz w_tmp1, w_tmp1
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);
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}
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_ => unreachable!(),
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}
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match dst {
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Location::GPR(x) => dynasm!(
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self
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; mov W(map_gpr(x).x()), w_tmp1
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),
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(
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self
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; str w_tmp1, [X(map_gpr(base).x()), disp as u32]
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)
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}
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_ => unreachable!(),
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}
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}
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Size::S64 => {
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match src {
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Location::Imm32(x) => dynasm!(self
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; b >after
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; data:
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; .qword x as i64
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; after:
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; ldr x_tmp2, <data
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; clz x_tmp1, x_tmp2
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),
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Location::GPR(x) => dynasm!(self
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; clz x_tmp1, X(map_gpr(x).x())
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),
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(self
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; ldr x_tmp1, [X(map_gpr(base).x()), disp as u32]
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; clz x_tmp1, x_tmp1
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);
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}
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_ => unreachable!(),
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}
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match dst {
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Location::GPR(x) => dynasm!(
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self
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; mov X(map_gpr(x).x()), x_tmp1
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),
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(
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self
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; str x_tmp1, [X(map_gpr(base).x()), disp as u32]
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)
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}
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_ => unreachable!(),
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}
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}
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_ => unreachable!(),
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}
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emit_clz_variant(self, sz, &src, &dst, false);
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}
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fn emit_tzcnt(&mut self, sz: Size, src: Location, dst: Location) {
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unimplemented!("instruction")
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emit_clz_variant(self, sz, &src, &dst, true);
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}
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fn emit_popcnt(&mut self, sz: Size, src: Location, dst: Location) {
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unimplemented!("instruction")
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dynasm!(
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self
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; brk 90 // TODO: Implement
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);
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}
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fn emit_movzx(&mut self, sz_src: Size, src: Location, _sz_dst: Size, dst: Location) {
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match (sz_src, src, dst) {
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@ -799,16 +911,15 @@ impl Emitter for Assembler {
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}
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_ => unreachable!(),
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}
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unimplemented!("instruction")
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}
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// TODO: These instructions are only used in FP opcodes. Implement later.
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fn emit_btc_gpr_imm8_32(&mut self, src: u8, dst: GPR) {
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unimplemented!("instruction")
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}
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fn emit_btc_gpr_imm8_64(&mut self, src: u8, dst: GPR) {
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unimplemented!("instruction")
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}
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fn emit_cmovae_gpr_32(&mut self, src: GPR, dst: GPR) {
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unimplemented!("instruction")
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}
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@ -1093,3 +1204,69 @@ impl Emitter for Assembler {
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);
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}
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}
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fn emit_clz_variant(assembler: &mut Assembler, sz: Size, src: &Location, dst: &Location, reversed: bool) {
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match sz {
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Size::S32 => {
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match *src {
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Location::GPR(src) => {
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dynasm!(
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assembler
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; mov w_tmp1, W(map_gpr(src).x())
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)
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}
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(
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assembler
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; ldr w_tmp1, [X(map_gpr(base).x()), disp as u32]
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)
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}
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_ => unreachable!()
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}
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match *dst {
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Location::GPR(dst) => {
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if reversed {
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dynasm!(assembler ; rbit w_tmp1, w_tmp1);
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}
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dynasm!(
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assembler
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; clz W(map_gpr(dst).x()), w_tmp1
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);
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}
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_ => unreachable!()
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}
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}
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Size::S64 => {
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match *src {
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Location::GPR(src) => {
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dynasm!(
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assembler
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; mov x_tmp1, X(map_gpr(src).x())
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)
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}
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Location::Memory(base, disp) => {
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assert!(disp >= 0);
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dynasm!(
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assembler
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; ldr x_tmp1, [X(map_gpr(base).x()), disp as u32]
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)
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}
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_ => unreachable!()
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}
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match *dst {
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Location::GPR(dst) => {
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if reversed {
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dynasm!(assembler ; rbit x_tmp1, x_tmp1)
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}
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dynasm!(
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assembler
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; clz X(map_gpr(dst).x()), x_tmp1
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);
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}
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_ => unreachable!()
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}
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}
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_ => unreachable!()
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}
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}
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